June 23: Round Table on Funding for Smart Systems & ECSEL (coordinator for SIE: Prof. E. Sangiorgi).
Protected: SIE2017 – Book of Abstracts
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The Round Table will be focused on the current situation of ECSEL JTI, with particular reference to the 2017 calls, its future evolution and the various funding possibilities at national and regional level. Ongoing projects and ideas under development for the 2017 calls will be mentioned with reference to those with Italian involvement.
Download the Program of the Round Table (last update: June 14, 2017)
Download the Accompanying Person Touristic Program (last update: June 14, 2017)
SIE2017 IEEE Distinguished Lectures
Wednesday, June 21, 2017
h. 14.30 – 15.10
CEA Research Director Past Chief Scientist
The Energy and Variability Efficient Era (E.V.E.) is ahead of us
Major power consumption reduction will drive future design of technologies and architectures that will request less greedy devices and interconnect systems. The electronic market will be able to face an exponential growth thanks to the availability and feasibility of autonomous and mobile systems necessary to societal needs. The increasing complexity of high volume fabricated systems will be possible if we aim at zero intrinsic variability, and generalize 3-dimensional integration of hybrid, heterogeneous technologies at the device, functional and system levels. Weighing on the world energy saving balance will be possible and realistic by maximizing the energy efficiency of co integrated Low Power and High Performance Logic and Memory devices.The future of Nanoelectronics will face the major concerns of being Energy and Variability Efficient (E.V.E.).
Simon Deleonibus, retired from CEA-LETI on Jan 1st 2016 as Chief Scientist after 30 years of Research on Micro Nanoelectronics Devices Architectures. Before joining CEA-LETI, he was with Thomson Semiconductors (1981-1986), where he developed and transferred to production advanced microelectronics devices and products. He gained his PhD in Applied Physics from Paris University (1982). He is Visiting Professor at Tokyo Institute of Technology (Tokyo, Japan) since 2014, National Chiao Tung University(Hsinchu, Taiwan) since 2015 and at Chinese Academy of Science (Beijing, PRC) since 2016.
He is distinguished CEA Research Director (2002), IEEE Distinguished Lecturer (2004), Fellow of the IEEE (2006), Fellow of the Electrochemical Society (2015).
He was awarded the titles of Chevalier de l’Ordre National du Mérite (2004) and Chevalier de l’Ordre des Palmes Académiques (2011), the 2005 Grand Prix de l’Académie des Technologies. He is member of the ITRS since 1998, the European Research Council Panel (2007), the Nanosciences Foundation Board of Trustees (2007). He was Associate Editor of IEEE Trans. on Elect. Dev. (2008-2014) and Member of the IEEE Electron Devices Society Board of Governors (01/2009 12/2014) and reelected (2016-2018); Chair of IEEE EDS Region 8 SRC (2015-2016).
He is currently Secretary of IEEE Electron Devices Society (2016-2017).
SIE2017 Invited Lecturers
Thursday, June 22, 2017
h. 14.00 – 14.40
Associate Professor at the National University of Singapore
Energy-Quality Scalable Adaptive VLSI Circuits and Systems – The Way towards the Next 10X Energy Reduction
In this talk, the concept of energy-quality (EQ) scalable systems is introduced and explored, as novel design dimension to scale down energy in integrated systems for the Internet of Things (IoT). EQ-scalable systems explicitly trade off energy and quality at different levels of abstraction (“vertically”), and sub-systems (“horizontally”), creating new opportunities to improve energy efficiency for a given task and expected “quality”.
The concept of quality slack, a taxonomy of techniques to trade off energy and quality, and a general EQ-scalable architecture are introduced. The generality of the EQ-scaling concept is shown through several examples, ranging from logic to analog circuits, to memories and Analog-Digital Converters. Challenges, opportunities and expected energy gains are discussed to gain an understanding of the potential of the EQ-scalable integrated circuits and systems. Ultimately, EQ scalable systems are expected to substantially improve the energy efficiency of systems for IoT, compensating the limited energy gains that will be offered by technology and voltage scaling in the decade ahead.
Massimo Alioto is Associate Professor at the Department of Electrical and Computer Engineering, National University of Singapore, where he leads the Green IC group and the Integrated Circuits and Embedded Systems area (60+ people). He has also held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan – Ann Arbor (2011-2012), University of California – Berkeley (2009-2011) and EPFL – Lausanne (2007).
He is (co)author of 230 publications on journals (80, mostly IEEE Transactions) and conference proceedings, and three books with Springer. His primary research interests include ultra-low power VLSI circuits, self-powered and wireless nodes, near-threshold circuits for green computing, widely energy-scalable VLSI circuits, circuit techniques for emerging technologies, and hardware cybersecurity.
Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE CASS (2010-2012), and Distinguished Lecturer (2009-2010). He is currently Associate Editor in Chief of the IEEE Transactions on VLSI Systems. He also serves or has served as Associate Editor of several journals (e.g., ACM Transactions on Design Automation of Electronic Systems, IEEE Transactions on CAS – part I/II). He served as Guest Editor of various journal special issues (including the up-coming issue on “Circuits and systems for the Internet of Things – from sensing to sensemaking” on IEEE Transactions on Circuits and Systems – part I). He was Technical Program Chair of the SOCC 2016, PRIME 2016, ICECS 2015, VARI 2015, ICECS 2013, NEWCAS 2012, ICM 2010 conferences, and Track Chair in several others (ICCD, ISCAS, ICECS, VLSI-SoC, APCCAS, ICM). He is currently member of the IEEE CASS Board of Governors. Prof. Alioto is an IEEE Fellow.
Thursday, June 22, 2017
h. 8.30 –9.10
Senior Scientist at Ecole Polytechnique Fédérale de Lausanne
Room-temperature blue emitting high-beta GaN nanobeam cavity lasers
Over the past few years recent advances in nanofabrication led to the emergence of dielectric nanocavities that can confine light to a nearly diffraction limited volume. By combining such cavities with a gain medium, the resulting nanolasers exhibit a peculiar emission compared to conventional lasers. In contrast to the traditional signatures of lasing—i.e., a sharp increase in the intensity in parallel with a narrowing of the emission spectrum, due to the amplification of stimulated emission—the lasing transition becomes blurred in the nanolaser case. This blurring occurs because spontaneous photon emission is efficiently coupled to the nanocavity mode. As a result, the conventional intensity increase and emission linewidth are not frequently observed in nanolasers. In this talk we will report on the main features of blue emitting high-quality factor (Q) III-nitride nanobeam photonic crystal cavities containing an InGaN/GaN quantum well (QW) gain medium. Transition from incoherent to coherent light emission is monitored using power-dependent second-order autocorrelation function measurements. Fabrication statistics performed on a second generation of blue nanobeam cavities show a twofold increase in the average Q value (> 4000) with a high fabrication yield thanks to the use of a single-step pattern transfer process. Interestingly, such statistical analysis also indicates that conventional disorder models could not explain the dominant contribution to experimental Q factors. Additionally, the introduction of a sidewall grating outcoupler increased the integrated far-field intensity of those structures by nearly one order of magnitude.
Raphaël Butté received the PhD degree from the University Claude Bernard, Lyon, France, in 2000 for his research on the structural and optoelectronic properties of hydrogenated nanostructured silicon thin films. After a three-year postdoctoral stay at the University of Sheffield where his research shifted to the optical properties of III-V semiconductors, he moved to Ecole Polytechnique Fédérale de Lausanne (EPFL) in 2004 in a newly established laboratory directed by Prof. Nicolas Grandjean. In 2010, he became a permanent member of staff and was promoted to the position of Senior Scientist in April 2016.
His current research activity mainly deals with microcavities, planar waveguides and photonic crystals made from III-nitride semiconductors.
He is the author of more than 90 scientific articles published in peer-reviewed international journals (> 3000 citations, h-index: 28) and 6 book chapters. He has given 26 invited talks in international conferences.
In 2012, he was one of the 149 scientists recognized by the Outstanding Referee program of the American Physical Society (APS) selected from a pool of roughly 60,000 currently active referees.
Thursday, June 22, 2017
h. 9.10 – 9.50
Richard M. DE LA RUE
Honorary Senior Research Fellow at the University of Glasgow
Array meta-surfaces for biomedical sensing at infra-red wavelengths
Richard De La Rue retired formally from the University of Glasgow in September 2010 and joined the Photonics Research Centre at the University of Malaya in April 2011, where he spent a year as Visiting Professor. In August 2012 he became Research Professor of Optoelectronics in the School of Engineering at the University of Glasgow – and completed his tenure in July 2014. He currently has the status of Honorary Senior Research Fellow (Professor Emeritus) in Optoelectronics – at the University of Glasgow.
He is Fellow of the European Optical Society; Fellow of the IEEE; Fellow of the OSA; Fellow of the Royal Academy of Engineering; Fellow of the Royal Society of Edinburgh and Fellow of the Institution of Engineering and Technology.
His Hirsch index, according to Google Scholar, is 56.
SIE2017 IEEE Fellow Lectures
Friday, June 23, 2017
h. 08.50 – 09.30
Full Professor at the University of Catania
CMOS Multistage Amplifiers
CMOS multistage amplifier design has relentlessly drawn remarkable research attention. Indeed, growing applications demanding high-gain, wide-bandwidth and fast-settling amplifiers in heavy-load and low-power conditions provide motivations for challenging efforts towards global performance enhancement. In this framework, three-stage and four-stage operational transconductance amplifiers (OTAs) are attractive for high-gain high-accuracy buffering/amplifying operation, owing to their speed, area and power efficiencies under low-voltage and low-power constraints. Their design however is not trivial. In this talk, design and optimization of multistage CMOS operational amplifiers in terms of architectures, frequency compensation techniques, Slew Rate, and other relevant issues are discussed in detail to provide a look at the latest results and future trends.
Salvatore Pennisi received the laurea degree in Electronic Engineering in 1992 and the Ph.D. degree in Electrical Engineering in 1997, both from the University of Catania, Italy. He is now full professor at the Dipartimento di Ingegneria Elettrica, Elettronica e Informatica of the University of Catania, where he teaches courses for first level and master laurea degrees and is presently the coordinator of the Laurea Magistrale Course in Electronic Engineering.
His main research interests include circuit theory and analog design with emphasis on low-voltage and current-mode techniques, multi-stage amplifiers with related frequency compensation, data converters and high-frequency distortion analysis in analog circuits. More recently, his research activities have involved driving circuits and techniques for liquid crystal displays and circuits for efficient energy harvesting. He is the (co)author of more than 90 international journal papers (mostly IEEE), over 130 conference proceedings, and is the co-author of the books CMOS Current Amplifiers (1999), Feedback Amplifiers: Theory and Design (2001) both edited by Kluwer Academic Publishers, and Liquid Crystal Display Drivers-Techniques and Circuits (Springer, 2009).
Prof. Pennisi is member of the IEEE CASS Analog Signal Processing Technical Committee and served as an Associate Editor of the IEEE Transactions on Circuits and Systems-Part II: Express Briefs and of the Wiley International Journal of Circuit Theory and Applications. He is involved in the technical committee of several conferences including IEEE ISCAS, IEEE NEWCAS, ESSCIRC, etc and has been the General Chair of PRIME 2017. Prof. Pennisi is an IEEE Fellow.
Friday, June 23, 2017
h. 09.30 – 10.10
Full Professor at Politecnico di Milano
DTC-Based Digital PLLs
Digital phase-locked loops (DPLLs) have emerged in last ten years as an important alternative to analog PLLs, also for fractional-N synthesis in wireless applications where a very demanding spectral purity is required. While in the initial implementations the key building block of DPLLs was a multibit time to digital converter (TDC), which is power consuming circuit analog to an ADC, record performance have been ultimately obtained by exploiting an architecture featuring a time arbiter, i.e. a single-bit TDC, driven by a multi bit digital-to-time converter (DTC). The key enabling idea is to exploit the dithering property of the thermal noise always present in a circuit.
The presentation reviews the path that has led to this approach, which epitomize how scaled CMOS technologies may enable powerful calibration techniques achieving unprecedented performance.
Carlo Samori received the Ph.D. in electrical engineering in 1995, from the Politecnico di Milano, Italy, where he is now a professor.
His research interests are in the area of RF circuits, in particular of design and analysis of VCOs and high performance frequency synthesizers. He has collaborated with several semiconductor companies. He is a co-author of more than 100 papers and of the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press, 2007). Prof. Samori has been a member of the Technical Program Committee (TPC) of the IEEE International Solid-State Circuits Conference and he is a member of the TPC of the European Solid-State Circuits Conference. He has been Guest Editor for the December 2014 issue of the Journal of Solid-State Circuits.
Carlo Samori is a Distinguished Lecturer of the IEEE Solid-State Circuits Society and an IEEE Fellow.